1. Technical Field
The invention relates to buffering received data on plesiochronous nodes of a data processing system and more particularly to application of elastic buffers in such nodes where the nodes are linked by extremely high speed unidirectional data links such as provided for the scalable coherent interface (SCI).
2. Description of the Related Art
In digital data processing systems, particularly multiple processor systems, the conventional backplane multi-drop bus has become a serious constraint on system performance because of throughput limitations, bus access contention problems and electro-magnetic interference generation. To move past the multidrop bus the Institute of Electrical and Electronics Engineers (IEEE) has established the IEEE Standard for Scalable Coherent Interface (IEEE Std 1596-1992) to provide computer bus like services using a collection of fast node to node unidirectional links for multiprocessor systems using a distributed coherent shared memory configuration.
The SCI and the similar IBM SCIL system provide local clocks, which are preferably tuned to a nominal transmission clock frequency, e.g. 500 Megahertz. No node is master of the system, and thus while the nodes preferably operate at the same clock speed, each node is clocked by a local oscillator. Oscillators are subject to unsynchronized drift with the result that each node actually operates at its own, varying frequency. Typically an allowance for difference between consecutive nodes (an external and an internal clock) must allow for a variation of 1000 ppm in frequency.
An SCI node is itself almost entirely synchronous. The only asynchronous part of the node is the first stage for receiving data. The clock for the received data is the same as the clock for the node which transmitted data.
SCI and SCIL provide for transmission of parallel data over the unidirectional links in delimited packets with the transmission clock for the data. These symbols are spaced by idle packets at a sufficient frequency to allow symbol skipping when required to realign the phase of a lower frequency receiving node to a higher frequency transmitting node. When a skip occurs, an idle symbol is discarded. Where the receiving node is faster, the opposite operation, i.e. idle symbol stuffing occurs. That is, an extra symbol is added to the packet sequence. The use of elastic buffers for skipping and stuffing operations to overcome phase drift is well known. Idle symbols are in fact sometimes called elasticity symbols.
Unfortunately, operation at high frequencies which are close to the physical limitations of a technology, such as 500 Megahertz for silicon based technology, can make idle symbol stuffing difficult if not impossible. To stuff a symbol, a node is called on to carry out two cycles in almost exactly the period allowed for one cycle. Such an operating speed may simply be unobtainable, even for short periods. It would be valuable to avoid the need to engage in symbol stuffing.